The present invention relates to a method for manufacturing a silicon wafer and a bonded wafer such as a bounded SOI (silicon on insulator) wafer and a direct bond wafer. More specifically, the present invention relates to a silicon wafer which reduces polishing sag generated in the peripheral portion of the wafer, a bonded SOI wafer and a direct bond wafer which have no periphery removing region or reduce it, and a manufacturing method thereof.
A typical process for manufacturing a silicon mirror wafer is known to have a slice step for slicing a silicon single crystal ingot in a wafer shape using a wire saw or an inner diameter slicer, a chamfering step for chamfering the peripheral portion of the wafer for preventing cracks or fractures of the sliced wafer, a lapping step for lapping the wafer using loose abrasives to enhance flatness, an etching step for etching the wafer using an acid solution or an alkaline solution to remove processing deformation, and a mirror polishing step for polishing at least one of the surfaces thereof.
In the mirror polishing step, since a hard silicon wafer is mirror finished with a soft polishing cloth by mechanochemical polishing, a region called polishing sag (hereinafter, also called peripheral sag) as shown in FIG. 5 exists in the peripheral portion thereof. The polishing sag which affects device fabrication is desirably eliminated to a minimum. Only mechanical polishing must be performed in order to thoroughly remove polishing sag. Even when using a processing method in a ductile mode which is a method for preventing crack damage by machining, the processing generates dislocation which must be removed by mechanochemical polishing. As a result, the polishing sag cannot be avoided.
Such a silicon mirror wafer is used to manufacture a bonded SOI wafer. The bonded SOI wafer is a technique for bonding two silicon wafers together via a silicon oxide film. As disclosed in Japanese Patent Publication No. Hei 5-46086, there has been known a method in which an oxide film is formed on at least one of the two wafers, the wafers are closely contacted with each other so as not to contain any foreign matters between the surfaces to be bonded, and they are subjected to a heat treatment at a temperature of 200 to 1200xc2x0 C. to enhance the bonding strength.
The bonded wafer whose bonding strength is enhanced by performing a heat treatment can be subjected to later grinding and polishing processes. The thickness of the device fabrication side wafer is reduced to a desired thickness by grinding and polishing to form an SOI layer for device forming.
Since both the wafer surfaces before being bonded are mirror finished by mechanochemical polishing as described above, polishing sag exists in the peripheral portion thereof. An unbonded region of, e.g., about 1 to 3 mm is generated in the peripheral portion of the bonded wafer manufactured by bonding both the wafers together.
When one of the wafers is ground and polished while the unbonded region remains, the unbonded region is separated in the process, so that damage or particle attachment adversely will affect the device forming region. The unbonded region must be removed previously.
Japanese Laid-Open Patent Publication No. Hei 6-176993 proposes a method for manufacturing a bonded wafer in which two silicon wafers are closely contacted with each other via an oxide film, a region including an unbonded region of the periphery of a bonded wafer whose bonding strength is enhanced by subjecting the silicon wafers to a heat treatment in an oxidizing atmosphere is ground from the front surface side of the bond wafer (a first silicon wafer as a device region) in the thickness direction to a portion immediately before a bonding interface between the bond wafer and the base wafer (a second silicon wafer as a support), the bond wafer is etched to the bonding interface so as to thoroughly remove the unbonded region, and the bond wafer is ground and polished to reduce its thickness to a desired thickness.
According to this method, the unbonded region can be removed without changing the shape of the base wafer. As a periphery removing width for thoroughly removing the unbonded region, a portion of at least 3 mm from the peripheral edge of the bond wafer is typically removed in view of safety.
Also is known a technique for reducing an unbonded region (Japanese Laid-Open Patent Publication No. Hei 11-26336) in which a joined wafer is subjected to a heat treatment in an oxidizing atmosphere so as to fill an unbonded region of the periphery thereof with a thermal oxide film. A thermal oxidation treatment must be performed at high temperatures for a long time in order to sufficiently fill the unbonded region with the thermal oxide film, and enough bonding strength cannot be obtained. As a further method, Japanese Patent Publication No. Hei 4-4742 describes a technique for removing an unbonded region in which two wafers are bonded together, and the peripheral portions of both the wafers are ground at the same time to reduce the diameter of the wafers.
This method can obtain an SOI wafer having no periphery removing region in an SOI layer, as disclosed in the Japanese Laid-Open Patent Publication No. Hei 6-176993. A wafer having a diameter larger than the standard diameter of an SOI wafer to be manufactured must be used as a raw material wafer.
In addition, there has been known a method for manufacturing a direct bond wafer in which silicon wafers are directly contacted with each other without interposing an oxide film, and they are subjected to a heat treatment to enhance the bonding strength. There is the same problem as that of the bonded SOI wafer with respect to the unbonded region of the peripheral portion of a thickness-reduced layer (bond layer).
In recent years, with high-integration and high-speed of semiconductor devices, the thickness of the SOI layer must be made smaller and improve the film thickness uniformity. Specifically, the film thickness and the film thickness uniformity of about 0.1xc2x10.01 xcexcm are required.
In order that the thin film SOI wafer having such a film thickness and film thickness uniformity is realized by a bonded wafer, the prior art process for reducing the thickness using grinding and polishing cannot be employed. As a new thin-film technique, there is developed a method called an ion implantation separation method (also called a Smart Cut (trademark) method) disclosed in Japanese Laid-Open Patent Publication No. Hei 5-211128.
This ion implantation separation method is a technique that comprises forming an oxide film on at least one of two silicon wafers, implanting at least one of hydrogen ions or rare gas ions into one of the silicon wafers (hereinafter, also called a bond wafer) from its upper surface to form a fine bubble layer (enclosed layer) inside the silicon wafer, bringing the ion-implanted surface into contact with the other wafer (hereinafter, also called a base wafer) via the oxide film, then subjecting the wafers to a heat treatment (separation heat treatment) to separate one of the wafer as a thin-film at the fine bubble layer as a cleavage plane (separating plane), and further subjecting them a heat treatment (bonding heat treatment) for firmly bonding them to obtain an SOI wafer.
In this method, silicon wafers can be directly bonded together without interposing an oxide film. This method is used not only in the case of bonding the silicon wafers together, but also in the case of implanting ions into a silicon wafer to be bonded to an insulator wafer such as quartz, silicon carbide, and alumina having different thermal expansion coefficients. There has recently been also known a method for manufacturing an SOI wafer in which hydrogen ions are excited to perform ion implantation in a plasma state for separation at room temperature without adding a special heat treatment.
According to this method, the separated plane is a good mirror surface, and an SOI wafer having extremely high uniformity of the SOI layer can be obtained relatively easily. The one separated wafer can also be reused, so that the material can be used effectively.
When the wafer is separated in a thin film form, the unbonded region of the peripheral portion is separated at the bonded surface. The above-mentioned step for removing an unbonded region of the peripheral portion is unnecessary. This is one of the important advantages of the ion implantation separation method along with the advantages of the film thickness uniformity of the SOI layer and recycle of the material.
When the peripheral portion of the SOI wafer manufactured by the ion implantation separation method is actually observed, the peripheral edge of the SOI layer is found to be positioned in a region at a distance of about 1 mm inwardly from the peripheral edge of the base wafer. This shows that the region at a distance of about 1 mm from the peripheral edge is not bonded and separated by the influence of polishing sag of the peripheral portions of the bonded wafers.
The unbonded width from the peripheral edge depends on the degree of the polishing sag. In the case of using a typical silicon mirror-polished wafer, the unbonded width is found to be typically about 1 mm and about 2 mm at the maximum.
As described above, the prior art bonded SOI wafer uses typical mirror-polished wafers as its raw material. Due to the peripheral sag of the wafer, the effective area of the SOI layer is reduced about 1 to 3 mm from the periphery. Otherwise, when attempting to make it possible to use the wafer to the maximum peripheral portion, this requires a process in which a wafer having a diameter slightly larger than the standard diameter of a typical mirror-polished wafer is prepared and bonded, and then, an unbonded region is removed to finish the wafer so as to have the standard diameter. Thus, the cost is increased, and the method cannot be a realistic manufacturing method for mass production of wafers.
A direct bond wafer manufactured by directly contacting silicon wafers with each other without interposing an oxide film has the same problem as that of the bonded SOI wafer with respect to the unbonded region of the peripheral portion of the thickness-reduced layer (bond layer).
The present invention has been made in such problems, and an object of the present invention is to provide a method for manufacturing a mirror-polished wafer with little peripheral sag by a relatively easy method. Another object of the present invention is to provide a method for manufacturing a bonded wafer having an SOI layer or a bond layer which has no periphery removing region or reduces it and a bonded wafer thereof by applying the above-mentioned method to a method for manufacturing a bonded SOI wafer or a direct bond wafer.
The present inventors have focused on the chamfering shape before mirror polishing in order to reduce polishing sag of a mirror polished wafer. In the chamfering width of the chamfered portions of a mirror polished wafer manufactured by a typical manufacturing process, as shown in FIG. 4, the size ratio of a chamfering width X1 of the wafer front surface side to a chamfering width X2 of the wafer back surface side is often X1=X2 (for example, 300xc2x1200 xcexcm). Chamfering is performed at least before mirror polishing the front surface. In some applications, X1 and X2 maybe set to different values. Also in this case, chamfering is typically performed before mirror polishing the front surface. In the name of mirror chamfering, the chamfered portion may be mirror polished after mirror polishing the front surface of the wafer. This is performed to chiefly mirror polish the chamfered portion for preventing particles from being generated, but does not vary the chamfering shape in the process.
The present inventors have focused on the chamfering process and envisaged that when the front surface side is chamfered again after mirror polishing the front surface of the wafer, part or all of the polishing sag portion can be included into the chamfering width, thereby making it possible to reduce polishing sag.
When the front surface side is not chamfered at all before polishing the front surface, the possibility of generating cracks or fractures becomes high during the other processes. The chamfering width previously provided in the chamfered portion of the front surface side before polishing the front surface of the wafer is smaller than the chamfering width of the back surface. Cracks and fractures can be prevented from being generated, and polishing sag can be reduced.
The above-mentioned method is applied to a method for manufacturing a bonded SOI wafer or a direct bond wafer. It is thus possible to manufacture a bonded wafer having an SOI layer or a bond layer which has no periphery removing region or reduces it.
In a method for manufacturing an SOI wafer, polishing sag of the peripheral portion is reduced. When the thickness of the SOI layer is below 1 xcexcm, without performing chamfering so as to increase the chamfering width of the front surface side of the SOI layer, the chamfered portion of the front surface of at least the SOI layer side is mirror chamfered or is mirror chamfered after tape polishing or soft grinding. It is thus possible to manufacture a bonded wafer having an SOI layer which has no periphery removing region or reduces it.